1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a metal layer.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
One of the most widespread technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer.
When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride, in the case of silicon-based devices.
Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high temperature source/drain formation and all silicide annealing cycles have been carried out.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.
For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level.
In the gate-first HKMG approach, a thin film of a silicon/germanium alloy (SiGe) is deposited on the surface of the silicon layer in order to adjust the transistor threshold voltage to a desired level. Since a portion of this thin film is included in the channel region of the FET, this SiGe thin film is also commonly referred to as “channel SiGe.”
Since epitaxial SiGe epitaxially grown on silicon experiences a compressive stress, SiGe alloys may also be used to introduce a desired stress component into the channel region of a P-channel FET. This is a desirable effect since the mobility of holes in the channel region of a P-channel FET is known to increase when the channel region experiences a compressive stress. Thus, trenches can be formed in portions of the source and drain regions of a FET adjacent to the channel region. An SiGe alloy, or a semiconductor alloy in general, can subsequently be epitaxially grown in the trenches. This semiconductor alloy is also commonly referred to as “embedded semiconductor alloy” or, in the particular case of an SiGe alloy, “embedded SiGe.”
Furthermore, in the HKMG technology, a thin “work function metal” layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN).
According to the gate-first HKMG approach, the gate structure is formed by depositing a stack of layers, which is subsequently appropriately patterned so as to obtain a gate structure of the desired size and dimensions. The stack of layers thus deposited ends with a cap layer formed on top of a gate material. The gate material is typically comprised of polysilicon. The gate cap layer, usually comprised of silicon nitride (Si3N4), is initially exposed and is used as a protection layer for the lower-lying layers during the gate patterning process and the following manufacturing stages. In order to permit silicidation of the polysilicon gate material, the cap layer is generally removed after forming the gate structure and before performing the silicidation process.
FIGS. 1a-1i show subsequent stages during a manufacturing process flow of a semiconductor structure including a FET according to the prior art.
FIG. 1a shows a semiconductor structure 100 comprising a semiconductor layer 102 in which an active region 102a has been formed. The active region 102a is laterally delimited by isolation regions 102b, which may be, for example, shallow trench isolations. The semiconductor layer 102 is supported by a substrate 101, which may be comprised of any suitable carrier.
A gate structure 160 of a transistor 150 has been formed on the surface of the active region 102a. The gate structure 160 shown in FIG. 1a has been formed according to the gate-first HKMG approach. Thus, the stack making up the gate structure 160 comprises an insulation layer 161 formed on the surface of the active region 102a, a gate metal layer 164, a gate material 162, and a cap layer 166 formed on the gate material 162 and exposing an upper surface to the outside.
The insulation layer 161, formed on the surface of the active region 102a, comprises a high-k material. The gate metal layer 164 is formed between the insulation layer 161 and the gate material 162 so as to adjust the transistor threshold voltage, as described above. The gate material 162, formed directly on the upper surface of the gate metal layer 164, typically comprises a semiconductor such as polysilicon. The cap layer 166 is formed at the top of the gate stack and is usually comprised of an insulating, relatively tough material, such as, for example, Si3N4.
FIG. 1b shows that, after forming the gate structure 160, a spacer structure 163 is formed on the sidewalls of the gate structure 160 in order to protect sensitive materials included in the gate stack, such as, for example, the metal of the metal layer 164. Thereafter, several series of implantations are performed in order to define source and drain regions 151 of the transistor 150 in the active region 102a. 
Initially, a first series of implantations is performed so as to define extension regions 151e and halo regions (not shown) of the source and drain regions 151 in the active region 102a. During this first series of implantations, the spacer structure 163 has an initial thickness, which is usually less than the final thickness.
Although not shown in the figures, a semiconductor alloy layer may be optionally embedded into the source/drain regions 151 after performing the halo/extension implantations. The embedded semiconductor alloy is used in order to provide a compressive stress component to the channel region of the FET 150. This is particularly advantageous in the case of P-channel FETs.
As shown in FIG. 1 c, the gate cap layer 166 is usually removed after performing the halo/extension implantations. The gate cap layer removal may be achieved by using an optical planarization layer (OPL) 170, as shown in FIG. 1 c. Alternatively, a sacrificial oxide spacer may be applied on the surface of the semiconductor structure 100.
The gate cap layer 166 is usually removed by performing a first etch (not shown) in the presence of the OPL 170. After removing the gate cap layer 166, the OPL 170 or the oxide spacer are removed by performing a second etch 183 shown in FIG. 1 d. 
FIG. 1 d shows the semiconductor structure 100 after performing the second etch process 183 aimed at removing the OPL or oxide spacer 170. The etch process 183 usually also removes a surface portion of the active region 102a. Therefore, the surface of the active region 102a is recessed after removing the OPL 170 with respect to the initial level. This is undesirable, since the thickness of the active region 102a is decreased by the etch process and, if a semiconductor alloy has been embedded in the source/drain regions 151, this is also partially removed.
FIG. 1e shows a subsequent stage in the manufacturing flow, wherein a further series of implantations is performed in order to define deep regions 151d of the source and drain regions 151. Before performing these deep region implantations, the spacer structure 163 may be appropriately broadened so as to serve as an implantation mask also during the deep implantations. After all implantations have been performed, the semiconductor structure 100 undergoes an annealing process aimed at activating the implanted ions and favoring recovery of the crystalline lattice of the semiconductor layer 102 after implantation damage. A channel region 155 of the transistor 150 is thus defined in the active region 102a. The channel region 155 is laterally defined by the source and drain regions 151.
After the activation annealing, a silicidation process is performed, the results of which are shown in FIG. 1f. During the silicidation process, a refractory metal layer (not shown) is deposited onto the exposed face of the semiconductor structure 100. Subsequently, a heat treatment is applied to the semiconductor structure 100 in order to promote a chemical reaction between the metal atoms of the deposited layer and the silicon atoms of the exposed surface of the semiconductor structure 100.
As a result of the silicidation, a metal silicide layer 153 is formed on the source and drain regions 151. Furthermore, a metal silicide layer 162a is formed after silicidation on top of the gate structure 160, thus forming an interface with the gate material 162 exposed before the deposition of the refractory metal layer. The formation of the metal silicide layer 162a is possible thanks to the gate cap layer removal process described above, which results in the gate material 162, typically polysilicon, being exposed to the outside before the deposition of the refractory metal layer. The metal silicide layers 153 and 162a typically comprise nickel silicide.
As shown in FIG. 1g, after formation of the silicide layers 153 and 162a, a stressed material layer 120 is deposited onto the surface of the semiconductor structure 100. Subsequently, a UV curing process is applied at a temperature ranging from 400-500° C.
An interlayer dielectric layer 130 is then deposited onto the stressed material layer 120, as shown in FIG. 1h. Thereafter, an etching process 181 is then applied, for example, in the presence of a patterned mask, in order to form via openings 172 and 174, as shown in FIG. 1i. The etching process 181 is calibrated so as to stop at the metal silicide layers 153 and 162a, so that openings 172 and 174 extend across the interlayer dielectric layer 130 and the stressed layer 120. Thus, openings 172 expose predetermined portions of the metal silicide layer 153 contacting the source and drain regions 151. On the other hand, via openings 174 expose predetermined portions of the metal silicide layer 162a contacting the gate material 162.
The method described above is affected by several drawbacks. First of all, a removal process of the gate cap layer 166 is necessary in order to permit formation of the metal silicide layer 162a contacting the gate material 162. This process, described above with reference to FIG. 1 c, is usually rather lengthy and complicated, thus resulting in increased manufacturing times and costs.
The gate cap layer removal process also results in undesirable damages to the surface of the layer on which the transistor is manufactured. As described above with reference to FIG. 1d, the etching process 183 performed in order to remove the coating layer 170 may likely erode a portion of the semiconductor layer 102, thus undesirably causing thinning of the active region 102a. If a semiconductor alloy, such as SiGe, has been embedded in the active region 102a of the transistor 150, this can also be undesirably removed by the etching process.
Furthermore, since the gate material 162 formed on top of the gate metal layer 164 is usually a semiconductor, for example polysilicon, a Schottky barrier is established at the interface between the gate metal layer 164 and the gate semiconductor material 162. This undesirably degrades the AC performance by limiting the circuit switching speed.
A method of solving the problem of the Schottky barrier is forming a so-called “fully silicided” gate, i.e., a gate wherein the metal silicide completely replaces the semiconductor gate material 162, so as to directly form an interface with the gate metal layer 164. An example of a manufacturing method of a fully silicided metal gate can be found in U.S. Pat. No. 6,831,887.
The methods of forming a fully silicided gate known from the prior art use the same silicidation step for forming the metal silicide layer 153 on the source/drain regions and the metal silicide layer 162a on top of the gate, as described above. Thus, the thickness of the gate metal silicide layer 162a cannot be increased without simultaneously increasing the thickness of the source/drain metal silicide layer 153. However, the thickness of the metal silicide layer 153 cannot be increased at will, since it must be considerably smaller than the thickness of the semiconductor layer 102.
Thus, there exists room for a simplified, more cost-effective manufacturing process of a transistor structure, resulting in a more effective contact to the gate electrode.